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? semiconductor msm7716 1/22 ? semiconductor msm7716 single rail linear codec general description the msm7716 is a single-channel codec cmos ic for voice signals that contains filters for linear a/d and d/a conversion. designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing dsps and digital wireless systems. the analog output signal can directly drive a ceramic type handset receiver. in addition, levels for analog outputs can be set by external control. features ? single power supply : +2.7 v to +3.6 v ? low power consumption operating mode : 24 mw typ. power down mode : 0.05 mw typ. ? digital signal input/output interface : 14-bit serial code in 2's complement format ? sampling frequency(fs) : 4 to 16 khz ? transmission clock frequency : fs 14 min., 2048 khz max. ? filter characteristics : when fs = 8 khz, complies with itu-t recommen- dation g. 714 ? built-in pll eliminates a master clock ? two input circuits in transmit section ? two output circuits in receive section ? transmit gain adjustable using an external resistor ? receive gain adjustable by external control 8 steps, 4 db/step ? transmit mic-amp is eliminated by the gain setting of a maximum of 36 db. ? analog outputs can drive a load of a minimum of 1 k w ; an amplitude of a maximum of 4.0 v pp with push-pull driving. ? built-in reference voltage supply ? package options: 32-pin plastic tsop (tsopi32-p-814-0.50-1k) (product name : msm7716ts-k) 30-pin plastic ssop (ssop30-p-56-0.65-k) (product name : MSM7716GS-K) e2u0043-28-82 this version: aug. 1998 previous version: nov. 1996
? semiconductor msm7716 2/22 block diagram main C + mao sw 1 pbin C + pbo sw 2 rc lpf 8th bpf 14 bit adconv tcont pll rtim rcont pwd logic pcmout 5th lpf 14 bit daconv rc lpf vol auto zero vr gen sg gen sgc sg C + sw 4 sw 4 vfo auxo C + aout+ C + sw 3 sw 3 aoutC pwi cont logic pwd sw cont vol cont sync bclk pcmin pdn den cdin dclk v dd ag dg
? semiconductor msm7716 3/22 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 main mao pbo pbin sgc ag auxo aout+ aoutC pwi vfo v dd dclk cdin den dg pcmin pcmout bclk sync pdn nc : no connect pin nc nc nc nc nc nc nc nc nc nc nc 32-pin plastic tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ag auxo pwi vfo nc nc v dd dclk nc dg pcmin sync pdn nc nc main mao pbin sgc nc : no connect pin aout+ aoutC nc cdin den nc pbo bclk nc pcmout nc 30-pin plastic ssop
? semiconductor msm7716 4/22 pin and functional descriptions main, mao transmit microphone input and the level adjustment. main is connected to the noninverting input of the op-amp, and mao is connected to the output of the op-amp. the level adjustment should be configured as shown below. during power saving and power down modes, the mao output is in high impedance state. C + main c1 microphone input r1 : variable r2 > 20 k w c1 > 1/(2 3.14 30 r1) (f) gain = r2/r1 < 63 r2 mao r1 sg pbin, pbo transmit handset input and the level adjustment. pbin is connected to the noninverting input of the op-amp, and pbo is connected to the output of the op-amp. the level adjustment should be configured as shown below. during power saving and power down, the pbo output is in high impedance state. v dd power supply pin for +2.7 to 3.6 v (typically 3.0 v). ag analog signal ground. dg ground pin for the digital signal circuits. this ground is separated from the analog signal ground in this device. the dg pin must be connected to the ag pin on the printed circuit board. C + pbin c2 r3 : variable r4 > 20 k w c2 > 1/(2 3.14 30 r3) (f) gain = r4/r3 < 63 r4 pbo r3 sg handset microphone input
? semiconductor msm7716 5/22 vfo receive filter output. the output signal has an amplitude of 2.0 v pp above and below the signal ground voltage when the digital signal of +3 dbm0 is input to pcmin. vfo can drive a load of 20 k w or more. this output can be externally controlled in the level range of 0 to C28 db in 4 db increments. during power saving or power down, vfo output is at the voltage level (v dd /2) of sg with a high impedance state. pwi, aout+, aoutC pwi is connected to the inverting input of the receive driver. the receive driver output is connected to the aoutC pin. thus, a receive level can be adjusted with the pins pwi, aoutC, and vfo described above. the output of aout+ is inverted with respect to the output of aoutC with a gain of 1. the output signal amplitudes are a maximum of 2.0 v pp . these outputs, above and below the signal ground voltage (v dd /2), can drive a load of a minimum of 1 k w with push-pull driving (a load connected between aout+ and aoutC). the output amplitudes are 4 v pp maximum during push-pull driving. these outputs can be mute controlled externally. these outputs are operational during power saving and output the sg voltage (v dd /2) in the high impedance state. auxo auxiliary receive filter output. the output signal is inverted with respect to the vfo output with a gain of 1. the output signal swings above and below the sg voltage (v dd /2), and can drive a minimum load of 0.5 k w with respect to the sg voltage. the output can be mute controlled externally. during power saving and power down, auxo outputs the sg voltage (v dd /2) in the high impedance state. bclk shift clock signal input for pcmin and pcmout. the frequency is equal to the data rate. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power-saving state.
? semiconductor msm7716 6/22 sync synchronizing signal input. in the transmit section, the pcm output signal from the pcmout pin is output synchronously with this synchronizing signal. this synchronizing signal triggers the pll and synchronizes all timing signals of the transmit section. in the receive section, 14 bits required are selected from serial input of pcm signals on the pcmin pin by the synchronizing signal. signals in the receive section are synchronized by this synchronizing signal. this signal must be synchronized in phase with the bclk. when this signal frequency is 8 khz, the transmit and receive section have the frequency characteristics specified by itu-t g. 714. the frequency characteristics for 8 khz are specified in this data sheet. for different frequencies of the sync signal, the frequency values in this data sheet should be translated according to the following equation: frequency values described in the data sheet the sync frequency values to be actually used 8 khz setting this signal to logic "1" or "0" drives the device to power-saving state. pcmin pcm signal input. a serial pcm signal input to this pin is converted to an analog signal synchronously with the sync signal and bclk signal. the data rate of the pcm signal is equal to the frequency of the bclk signal. the pcm signal is shifted at a falling edge of the bclk signal. the pcm signal is latched into the internal register when shifted by 14 bits. the top of the data (msd) is identified at the rising edge of sync. the input signal should be input in the 14-bit 2's complement format. the msd bit represents the polarity of the signal with respect to the signal ground.
? semiconductor msm7716 7/22 pcmout pcm signal output. the pcm output signal is output from msd in sequential order, synchronously with the rising edge of the bclk signal. msd may be output at the rising edge of the sync signal, depending on the timing between bclk and sync. this pin is in high impedance state except during 14-bit pcm output. it is also high impedance during power saving or power down mode. a pull-up resistor must be connected to this pin, because its output is configured as an open drain. the output coding format is in 14-bit 2's complement. the msd represents a polarity of the signal with respect to the signal ground. table 1 input/output level +full scale +1 0 Cfull scale pcmin/pcmout msd 0111 1111 1111 11 0000 0000 0000 01 0000 0000 0000 00 1000 0000 0000 00 C1 1111 1111 1111 11 pdn power down control signal input. a digital "l" level drives both transmit and receive circuits to a power down state. the control registers are set to the initial state. sgc connection of a bypass capacitor for generating the signal ground voltage level. connect a 0.1 m f capacitor with excellent high frequency characteristics between the ag pin and the sgc pin.
? semiconductor msm7716 8/22 den, dclk, cdin serial control ports for the microcontroller interface. writing data to the 8-bit control register enables control of the receive output level and the signal path. den is the "enable" signal pin, dclk is the data shift clock input pin, and cdin is the control data input pin. when powered down (pdn = 0), the initial values are set as shown in tables 2, 3, and 4. the initial values are held unless the control data is written after power-down release. the control data is shifted at the rising edge of the dclk signal and latched into the internal control register at the rising edge of the den signal. when the microcontroller interface is not used, these pins should be connected to dg. the bit map of the 8-bit control register is shown below. b7 sw1 b6 sw2 b5 sw3 b4 sw4 b3 b2 vol1 b1 vol2 b0 vol3
? semiconductor msm7716 9/22 absolute maximum ratings parameter power supply voltage analog input voltage digital input voltage storage temperature symbol v dd v ain v din t stg condition ag = dg = 0 v ag = dg = 0 v ag = dg = 0 v rating C0.3 to +7.0 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C55 to +150 unit v v v c recommended operating conditions parameter power supply voltage operating temperature analog input voltage high level input voltage low level input voltage clock frequency sync pulse frequency clock duty ratio digital input rise time digital input fall time sync pulse setting time high level sync pulse width *1 low level sync pulse width *1 pcmin setup time pcmin hold time digital output load dclk pulse width den setting time 1 den setting time 2 cdin setup time cdin hold time analog input allowable dc offset allowable jitter width symbol v dd ta v ain v ih v il f c f s d c t ir t if t xs , t rs t wsh t ds t dh r dl t wcl t cdl t cdh t cds t cdh v off t sx , t sr c dl t wch t dcl t dch condition gain = 1 sync, bclk, pcmin, pdn, den, dclk, cdin bclk sync bclk sync, bclk, pcmin, pdn, den, dclk, cdin bclk ? sync, see fig.1 sync, see fig.1 refer to fig.1 refer to fig.1 pull-up resistor dclk low width, see fig.2 dclk ? den, see fig.2 dclk ? den, see fig.2 see fig.2 see fig.2 transmit gain stage, gain = 0 db sync, bclk sync ? bclk, see fig.1 dclk high width, see fig.2 den ? dclk, see fig.2 den ? dclk, see fig.2 transmit gain stage, gain = 20 db min. 2.7 C30 0.45 v dd 0 14 fs 4.0 40 100 1 bclk 100 100 0.5 50 50 50 50 50 C100 100 50 50 50 C10 typ. 3.0 +25 8.0 50 max. 3.6 +85 1.4 v dd 0.16 v dd 128 fs 16 60 50 50 +100 1000 100 +10 unit v c v pp v v khz khz % ns ns ns ns ns k w ns ns ns ns mv ns ns pf mv t wsl sync, see fig.1 1 bclk *1 for example, the minimum pulse width of sync is 488 ns when the frequency of bclk is 2048 khz.
? semiconductor msm7716 10/22 recommended operating conditions (continued) electrical characteristics dc and digital interface characteristics parameter digital output delay time symbol t sd t xd1 t xd2 t xd3 min. 20 20 20 20 typ. max. 100 100 100 100 unit ns condition c l = 50 pf + 1 lsttl pull-up resistor = 500 w parameter power supply current high level input voltage low level input voltage high level input leakage current low level input leakage current digital output low voltage digital output leakage current input capacitance symbol i dd1 i dd2 i dd3 v ih v il i ih i il v ol i o condition operating mode, no signal power-saving mode, pdn = 1, sync, bclk ? off power-down mode, pdn = 0 pcmout pull-up resistor = 500 w min. 0.45 v dd 0.0 0.0 typ. 10.0 8.0 6.0 0.01 0.2 max. 17.0 13.0 11.0 0.05 v dd 0.16 v dd 2.0 0.5 0.4 10 unit ma ma ma v v m a m a v m a v dd = 3.6 v v dd = 3.0 v c in 5pf (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) ma sync, bclk, pcmin, den, cdin, dclk, pdn
? semiconductor msm7716 11/22 transmit analog interface characteristics receive analog interface characteristics input resistance output load resistance output load capacitance output amplitude offset voltage r inx r lgx c lgx v ogx v osgx main, pbin gain = 1 10 20 C0.7 C20 30 +0.7 +20 m w k w pf v mv mao, pbo with respect to sg parameter symbol condition min. typ. max. unit (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) output resistance output load resistance output load capacitance r oao r lvo r lao c lao auxo, aout+, aout- 20 0.5 10 50 w k w k w pf vfo with respect to sg output amplitude offset voltage v oao v osa C1.0 C100 +1.0 +100 v mv auxo, aout+, aoutC (each) with respect to sg output open auxo, aout+, aoutC, vfo with respect to sg auxo, aout+, aoutC, vfo with respect to sg parameter symbol condition min. typ. max. unit (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) r ovo vfo 100 w
? semiconductor msm7716 12/22 ac characteristics condition (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) parameter symbol min. typ. max. unit transmit frequency response (expected value) loss t1 level (dbm0) 60 20 freq. (hz) loss t2 300 C0.15 +0.2 loss t3 1020 reference db 0 loss t4 2020 C0.15 +0.2 loss t5 3000 C0.15 +0.2 loss t6 3400 0 0.8 receive frequency response (expected value) loss r1 300 C0.15 +0.2 loss r2 1020 reference loss r3 2020 C0.15 +0.2 db 0 loss r4 3000 C0.15 +0.2 loss r5 3400 0.0 0.8 sd t1 58 3 sd t2 58 0 sd t3 58 C10 transmit signal to distortion ratio (expected value) 1020 db sd t4 48 C20 *1 sd t5 38 C30 sd r1 58 sd r2 58 sd r3 58 receive signal to distortion ratio (expected value) 1020 db sd r4 48 *1 sd r5 38 3 0 C10 C20 C30 sd t6 28 C40 sd t7 18 C50 sd r6 28 C40 sd r7 18 C50 overall frequency response loss 1 60 20 loss 2 300 C0.2 +0.4 loss 3 1020 reference db 0 loss 4 2020 C0.2 +0.4 loss 5 3000 C0.2 +0.4 loss 6 3400 0 1.6 sd 1 55.9 3 sd 2 55.9 0 sd 3 55.9 C10 overall signal to distortion ratio 1020 db sd 4 45.9 C20 *1 sd 5 35.9 C30 sd 6 25.9 C40 sd 7 15.9 C50 analog to analog analog to analog *1 psophometric filter is used.
? semiconductor msm7716 13/22 ac characteristics (continued) condition (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz) 3 C10 C40 C50 C55 transmit gain tracking (expected value) gt t1 C0.3 +0.01 +0.3 gt t2 reference gt t3 1020 C0.3 0.00 +0.3 db gt t4 C0.6 C0.03 +0.6 gt t5 C1.2 +0.15 +1.2 receive gain tracking (expected value) gt r1 C0.3 C0.06 +0.3 gt r2 reference gt r3 1020 C0.3 C0.02 +0.3 db gt r4 C0.6 C0.02 +0.6 gt r5 C1.2 C0.27 +1.2 3 C10 C40 C50 C55 3 C10 C40 C50 C55 overall gain tracking gt 1 C0.4 +0.01 +0.4 gt 2 reference gt 3 1020 C0.3 0.00 +0.8 db gt 4 C1.3 C0.03 +1.3 gt 5 C1.6 C0.15 +1.6 analog to analog
? semiconductor msm7716 14/22 ac characteristics (continued) absolute level (initial level) nidle t C76 C74 dbmop nidle r C76 av t 0.338 0.350 0.362 av r 0.483 0.500 0.518 vrms 1020 absolute delay av tt C0.2 +0.2 0 av rt C0.2 +0.2 t d 1020 0.6 ms 0 a to a bclk = 64 khz transmit group delay t gd t1 0.325 t gd t2 0.175 0ms *3 t gd t3 0.325 receive group delay 0.00 0.125 ms 0 0.12 0.325 C74 transmit idle channel noise (expected value) ain: no signal *1 db db v dd = 3.0 v ta = 25c v dd = +2.7 to 3.6 v ta = C30 to 85c absolute level (deviation of temperature and power) *2 500 600 to 2600 2800 crosstalk attenuation cr t 7585 cr r 80 1020 db 0 trans ? recv recv ? trans t gd r1 t gd r2 2800 *3 70 condition parameter symbol min. typ. max. unit level (dbm0) freq. (hz) (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) receive idle channel noise (expected value) 500 to 2600 nidle a C70 C66 dbmop overall idle channel noise ain: no signal *1 *1 psophometric filter is used. *2 avt is defined at mao and pbo-pcmout. avr is defined at pcmin-vfo. vol = 0 db *3 minimum value of the group delay distortion
? semiconductor msm7716 15/22 ac characteristics (continued) *1 measured inband. dis 4.6 khz to 30 32 db vol gain setting value g v5 C17 C16 C15 g v6 C21 C20 C19 g v7 C25 C24 C23 g v8 C29 C28 C27 db discrimination 0 0 to 4000 hz s 300 to C37.5 C35 dbm0 out-of-band spurious 0 4.6 khz to imd fa = 470 C52 C40 dbm0 intermodulation distortion C4 2fa C fb psr t 0 to 30db power supply noise rejection ratio 50 mv pp *1 psr r 72 khz 3400 fb = 320 50 khz 100 khz condition parameter symbol min. typ. max. unit level (dbm0) freq. (hz) (fs = 8 khz, v dd = 2.7 v to 3.6 v, ta = C30c to +85c) g v4 C13 C12 C11 g v3 C9 C8 C7 g v2 C5 C4 C3 g aux C1.0 0 +1.0 auxiliary output gain 1020 0 vfo to auxo db 1020 0 set at C 4 db C8 db C12 db C16 db C20 db C24 db C28 db referenced to 0 db setting
? semiconductor msm7716 16/22 timing diagram pcm data output timing bclk 12345678910 sync pcmout d9 d10 d11 d12 d13 d14 msd t xs t sx t wsh t sd t xd1 t xd2 t xd3 bclk sync pcmin transmit timing receive timing 11 when t xs 1/2 ? fc, the delay of the msd bit is defined as t xd1 . when t sx < 1/2 ? fc, the delay of the msd bit is defined as t sd . 12 13 14 15 16 17 d2 d3 d4 d5 d6 d7 d8 12345678910 d9 d10 d11 d12 d13 d14 msd t rs t sr t wsh t ds 11 12 13 14 15 16 17 d2 d3 d4 d5 d6 d7 d8 t dh t wsl t wsl figure 1 basic timing diagram mcu interface timing t cdl t dcl t cdh t dch t wch t wcl dclk 1 2345678910111213 den b3 b4 b5 b6 b7 b2 b1 b0 cdin t cdh t cds figure 2 mcu interface timing diagram
? semiconductor msm7716 17/22 functional description control data description sw1, sw2 - - control bits for the transmit speech path switch. the ad converter input is selected according to the bit data shown in table 2. table 2 state sw2 sw1 ad converter input remarks t1 0 0 no signal (muting state) t2 0 1 input signal to main at initial setting t3 1 0 input signal to pbin t4 1 1 addition signal of both main and pbin the gain of each input drops about 6 db sw3, sw4 - - control bits for the receive speech path switch. the control should be performed according to table 3. table 3 state sw3 aout+, aoutC output auxo output r1 0 sg sg r2 1 pwi sg r3 0 sg da r4 1 pwi da remarks at initial setting da: da converter output. sg: signal ground voltage. sw4 0 0 1 1 vol1, vol2, vol3 - - - control bits for the receive signal output level. by controlling these bits, the output levels of vfo and auxo can be controlled according to table 4. table 4 vol1 vol2 vol3 receive signal gain remarks 0 0 0 0 db at initial setting 0 0 1 C4 db 0 1 0 C8 db 0 1 1 C12 db 1 0 0 C16 db 1 0 1 C20 db 1 1 0 C24 db 1 1 1 C28 db
? semiconductor msm7716 18/22 application circuit pcmout pcmin main mao pbin 0.1 m f pcm output pcm input 8 khz sync pulse input power down control input "1" = operation "0" = power down 1 m f 20 k w msm7716 pbo bclk sync +3 v pdn aoutC sgc ag dg v dd 0 v +3 v microphone analog input analog output* dclk 0 to 10 w 20 k w 1 m f 20 k w handset analog input 20 k w 10 m f vfo pwi 1 m f 20 k w addition signal input 20 k w 20 k w aout+ analog inverted output* auxo auxiliary output* 1 k w pcm shift clock input den cdin controller * the swing of the analog output signal is a maximum of 1.0 v above and below the v dd /2 offset level. 1 m f +
? semiconductor msm7716 19/22 application information digital pattern for 0 dbm0 the digital pattern for 0 dbm0 is shown below. (sync frequency = 8 khz, signal frequency = 1 khz) sample no. s1 s2 s3 s4 s5 s6 s7 s8 msd d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 0 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 0 sg s1 s2 s3 s4 s5 s6 s7 s8
? semiconductor msm7716 20/22 notes on use ? to ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. ? connect the ag pin and the dg pin as close as possible. connect to the system ground with low impedance. ? mount the device directly on the board when mounted on pcbs. do not use ic sockets. if the use of ic socket is unavoidable, use the short lead type socket. ? when mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. ? keep the voltage on the v dd pin not lower than C0.3 v even instantaneously to avoid latch- up that may otherwise occur when power is turned on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
? semiconductor msm7716 21/22 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop i 32-p-814-0.50-1k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.27 typ. mirror finish
? semiconductor msm7716 22/22 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop30-p-56-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.19 typ. mirror finish

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